In semiconductor circuit devices, finer pattern techniques are being developed and integration densities are increasing. However, with miniaturization, designers must also be concerned with unwanted parasitic components which decrease the operating speed of the devices. Another impediment to miniaturization is the alignment requirements for emitters and emitter isolation walls, which result in increased emitter-base junction size and a correspondingly larger base-collector junction size. These larger than desired junction areas, besides limiting device reduction efforts, can introduce unwanted parasitic capacitance which limits the device or circuit performance.
FIG. 1 shows a conventional lateral bipolar transistor 20. An N-type buried collector region 22 is selectively formed in a P-type semiconductor substrate 21. After field oxide regions 23 and 24 and collector isolation region 27 are formed by any known technique, a P-type base region 25 is formed at the surface of the N-type collector region 22. A polysilicon layer is formed and selectively doped P-type for base contact region 26.
Thereafter, an isolation trench is etched and filled with an oxide or other insulator 31 to form an emitter region 30. Polysilicon regions 28 and 29 are then doped and diffused down to form N+-type emitter region 30, an N-type emitter contact region 28, and N-type collector contact region 29. Surface insulation layer 32 is formed and patterned to open metalization contact areas for the base, emitter and collector regions, respectively. A silicide layer 33, 34 and 35 may be applied to enhance the electrical characteristics of the contact regions between the polysilicon and device contact metalization.
With regards to the bipolar transistor described in FIG. 1, it should be noted that the distance between field oxide region 24 and collector insulation wall 27 is limited to a critical variance dimension of at least about 1.8 microns, due to current manufacturing variances of approximately 0.3 microns in alignment. Accordingly, in the device of FIG. 1, if the distance between field oxide region 24 and collector isolation wall 27 is less than the critical variance dimension of approximately 1.8 microns, when the emitter isolation walls 31 are etched, the base region 26 can be totally pinched off due to alignment variances. That is, isolation wall 31 can come into contact with field oxide region 24, thus pinching-off the base contact area 26.
This alignment problem can be minimized by using a circular base contact region. However, such a solution would increase the overall size of the device as well. Due to this critical variance dimension of approximately 1.8 microns of the base region 25, there will be larger than desirable base-collector junction capacitance, extrinsic base resistance, and overall transistor size.